RV1106 is a highly‑integrated vision‑processor SoC designed for IPC applications, especially for AI‑related scenarios. It is built around a single‑core 32‑bit ARM Cortex‑A7 core with integrated NEON and FPU. It features 32 KB instruction cache, 32 KB data cache and 128 KB unified L2 cache. The on‑chip NPU supports mixed‑precision operations of INT4/INT8/INT16 with computing power up to 0.5 or 1 TOPS. With excellent compatibility, the NPU enables easy conversion of network models developed on frameworks including TensorFlow, MXNet, PyTorch and Caffe.
RV1106 adopts a new‑generation fully hardware‑based ISP supporting up to 5‑megapixel resolution, implementing algorithm accelerators such as HDR, 3A, lens‑shading correction, 3D noise reduction, 2D noise reduction, sharpening, dehazing and gamma correction. Equipped with two MIPI CSI interfaces and one DVP interface, it can build a system that receives video data from three camera sensors simultaneously. The built‑in video encoder supports H.265/H.264 encoding and multi‑stream encoding. With this capability, camera video can be encoded at higher resolution and stored in local memory, while another lower‑resolution video stream is transmitted to cloud storage. An intelligent video engine with 22 computing units is integrated to accelerate video processing. RV1106 embeds 16‑bit DDR3L DRAM to meet high‑memory‑bandwidth requirements. It also integrates on‑chip RTC, power‑on reset circuit, audio codec and MAC‑PHY.
‑ Single‑core ARM Cortex‑A7
‑ Full implementation of ARM v7‑A instruction‑set architecture
‑ ARM Neon advanced SIMD
‑ Independently‑integrated NEON and FPU
‑ 32 KB L1 instruction cache and 32 KB L1 data cache
‑ 128 KB unified L2 cache for Cortex‑A7
‑ Supports TrustZone technology
‑ One independent voltage domain for Dynamic Voltage and Frequency Scaling
‑ On‑chip internal memory
‑ BootRom
‑ System boot support from SPI‑interface devices
